IP2022 Data Sheet www.ubicom.com 39 encoded in the instruction. The remaining three bits come
from the PA2:0 bits of the STATUS register. Figure 4-10 shows the format of the instructions that clear,
set, and test individual bits within registers. The register is
specified by the “fr” field, and a 3-bit field in the instruction
selects one of the eight bits in the register. Figure    4-11    shows    the    format    of    the    remaining
instructions. 4.2.2 Instruction Types The instructions are grouped into the following functional
categories: • Logical instructions • Arithmetic and shift instructions • Bit operation instructions • Data movement instructions • Program control instructions • System control instructions Logical Instructions Each    logic    instruction    performs    a    standard    logical
operation     (AND,     OR,     exclusive     OR,     or     logical
complement) on the respective bits of the 8-bit operands.
The result of the logic operation is written to W or to the
data memory location specified by the “fr” field. All of these instructions take one clock cycle for execution. Arithmetic and Shift Instructions Each arithmetic or shift instruction performs an operation
such as add, subtract, add with carry, subtract with carry,
rotate  left  or  right  through  carry,  increment,  decrement,
clear  to  zero,  or  swap  high/low  nibbles.  The  compare
(cmp)   instruction   performs   the   same   operation   as
subtract, but it only updates the C, DC, and Z flags of the
STATUS    register;    the    result    of    the    subtraction    is
discarded. There    are    instructions    available    that    increment    or
decrement a register and simultaneously test the result. If
the 8-bit result is zero, the next instruction in the program
is  skipped.  These  instructions  can  be  used  to  make
program    loops.    There    are    also    compare-and-skip
instructions    which   perform    the    same    operation    as
subtract, then perform a conditional skip without affecting
either  operand  or  the  condition  flags  in  the  STATUS
register. All of the arithmetic and shift instructions take one clock
cycle for execution, except in the case of the test-and-skip
instructions when the tested condition is true and a skip
occurs,  in which case  the  instruction  takes at least two
cycles. If a skip instruction is immediately followed by a loadh,  loadl,  or  page  instruction  (and  the  tested condition is true) then two instructions are skipped and the
operation   consumes   three   cycles.   This   is   useful   for
skipping  over  a  conditional  branch  to  another  page,  in
which a page instruction precedes a jmp instruction. If
several page or loadh/loadl instructions immediately
follow a skip instruction, then they are all skipped plus the
next instruction and a cycle is consumed for each. These
“extended skip instructions” are interruptible, so they do
not affect interrupt latency. Bit Operation Instructions There are four bit operation instructions: • setb—sets a single bit in a data register without af- fecting other bits • clrb—clears a single bit in a data register without af- fecting other bits • sb—tests a single bit in a data register and skips the next instruction if the bit is set • snb—tests a single bit in a data register and skips the next instruction if the bit is clear All of the bit operation instructions take one clock cycle for
execution, except for test-and-skip instructions when the
tested condition is true and a skip occurs. Data Movement Instructions A data movement instruction moves a byte of data from a
data memory location to either the W register or the top of
stack, or it moves the byte from either the W register or the
top of  stack to a  data memory location.  The location  is
specified  by  the  “fr”  field.  The  SPH/SPL  register  pair
points to the top of stack. This stack is independent of the
hardware stack used for subroutine call and return. 15 13 12 0 Opcode                            Entry Point Address (“addr13”)
Figure 4-9  Jump and Call Instruction Format 15 12 11 9 8 0 Opcode Bit                                                               “fr” Field
Figure 4-10  Bit Operation Instruction Format 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0                                                                 Opcode
Figure 4-11  Miscellaneous Instruction Format