IP2022 Data Sheet www.ubicom.com 35 4.1 Addressing Modes The  arithmetic and  logical instructions have one  or two
operands. The two-operand instructions implicitly use the
W  register  as  one  of  the  operands.  The  one-operand
instructions  and one  of the  two operands used  by  two- operand     instructions     access     data    memory     using
addressing  modes.  A  9-bit  field  within  the  instruction,
called the “fr” field, specifies the addressing mode and the
address (in the case of direct addressing) or the address
offset (in the case of indirect-with-offset addressing), as
shown in Table 4-1. Table 4-1  Addressing Mode Summary “fr” Field Mode Syntax Effective Address (EA) Restrictions 000000000 Indirect mov w,(ip)
mov (ip),w IPH || IPL 0x020 < EA < 0xFFF 00nnnnnnn Direct, special-
purpose registers mov w,fr
mov fr,w nnnnnnn 0x002 < EA < 0x07F 01nnnnnnn Direct, global
registers mov w,fr
mov fr,w 0x080 + nnnnnnn 0x080 < EA < 0x0FF 10nnnnnnn Indirect with offset,
data pointer mov w,offset(dp)
mov offset(dp),w DPH || DPL + nnnnnnn 0x000 < nnnnnnn < 0x07F
0x020 < EA < 0xFFF 11nnnnnnn Indirect with offset,
stack pointer mov w,offset(sp)
mov offset(sp),w SPH || SPL + nnnnnnn 0x000 < nnnnnnn < 0x07F
0x020 < EA < 0xFFF