IP2022 Data Sheet
www.ubicom.com
3
1.1
Key Features
Internet Processor Capabilities
Foundation for Highly Flexible Connectivity Solution
•
100 MIPS performance @100 MHz
•
Predictable execution rate for hard real-time applica-
tions
•
Fast and deterministic 3-cycle (30ns @100MHz) in-
ternal interrupt response
•
Hardware save/store of key registers
•
Functions implemented via software tightly coupled
with hardware assist peripherals
Multiple Networking Protocols and Physical Layer
Support Hardware
•
Two full-duplex high speed serial bus
interfaces - serializer/deserializer (SERDES) channels
–
Flexible to support 10Base-T, GPSI, SPI, UART,
USB protocols
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Two channels for protocol bridging
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On-chip squelch function for 10Base-T Ethernet
•
Four hardware LFSR (Linear Feedback Shift Regis-
ter) units
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CRC generation/checking
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Data whitening
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Encryption
Network Software Package
•
Integrated all software-based TCP/IP protocol stack
and Ethernet MAC
•
RFC-compliant stack
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Supporting a range of protocol stack layers
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Flash file system
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Serial I/O and Ethernet drivers
•
Embedded networking application layer
•
IpOS™ operating system
•
IpModule™ configuration tool
On-Chip Memory
•
64-Kbyte (32K × 16) program flash memory
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16-Kbyte (8K × 16) program/data RAM
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4-Kbyte linear-addressed data RAM
•
Self-programming with built-in charge pump: instruc-
tions to read, write, and erase flash memory
•
Addresses up to 2 Mbytes of external memory
(128-Kbytes linear)
CPU Features
•
RISC engine core with DC to 100 MHz operation
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10 ns instruction cycle
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Compact 16-bit fixed-length instructions
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Single-cycle instruction execution on most instruc-
tions (3 cycles for jumps and calls)
•
Sixteen-level hardware stack for high-performance
subroutine linkage
•
8 × 8 signed/unsigned single-cycle multiply
•
Pointers and stack operation optimized for C compiler
•
Uniform, linear address space (no register banks)
General-Purpose Hardware Peripherals
•
Two 16-bit timers with 8-bit prescalers supporting:
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Timer mode
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PWM mode
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Capture/Compare mode
•
Parallel host interface, 8/16-bit selectable for use as a
communications coprocessor
•
External memory interface
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One 8-bit timer with programmable 8-bit prescaler
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One 8-bit real-time clock/counter with programmable
15-bit prescaler and 32 kHz crystal input
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Watchdog timer with prescaler
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On-chip PLL clock multiplier with pre- and post-divider
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100 MHz on-chip clock from 2 MHz ext. crystal
•
10-bit, 8-channel ADC with 1/2 LSB accuracy
•
Analog comparator with hysteresis enable/disable
•
Brown-out minimum supply voltage detector
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External interrupt inputs on 8 pins (Port B)
Sophisticated
Power
and
Frequency/Clock
Management Support
•
Operating voltage of 2.3V to 2.7V
•
Switching the system clock frequencies between dif-
ferent clock sources
•
Changing the core clock using a selectable divider
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Shutting down the PLL and/or the OSC input
•
Dynamic CPU speed control with speed instruction
•
Power-On-Reset (POR) logic
Flexible I/O
•
52 I/O Pins
•
2.3V to 3.3V symmetric CMOS output drive
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5V-tolerant inputs
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Port A pins capable of sourcing/sinking 24 mA
•
Optional I/O synchronization to CPU core clock
