IP2022 Data Sheet www.ubicom.com 29 3.8.3 TRIM0 Register 15 12 11 10 9 7 6 5 4 3 2 1 0 SQUELT3:0 SQUELT5    FPERT CMPT2:0 SQUELT4  VCOT3 BORT1:0 VCOT2:0 Figure 3-22  TRIM0 Register SQUELT5:0 SERDES squelch trim bits FPERT Controls flash block pulse erase time, for both self-programming ferase and the FERASE com-
mand from the ISD/ISP interface 0 =  20 ms
1 =  10 ms CMPT2:0 Comparator offset trim bits VCOT3:0 PLL VCO frequency trim bits BORT2:0 Brown-out detector trim bits