IP2022 Data Sheet www.ubicom.com 27 3.8.1 FUSE0 Register 15 14 13 12 11 9 8 7 6 5 3 2 0 XTAL RTCLK POUT1:0 PIN2:0 Reserved WUDP2:0 WUDX2:0 Figure 3-20  FUSE0 Register XTAL OSC2 crystal drive output 0 =  Enabled
1 =  Disabled RTCLK RTCLK2 crystal drive output 0 =  Enabled
1 =  Disabled POUT1:0 Specifies PLL clock multiplier postscaler divisor 00 =  1
01 =  2
10 =  3
11 =  4 PIN2:0 Specifies PLL clock multiplier prescaler divisor 000 =  1
001 =  2
010 =  3
011 =  4
100 =  5
101 =  6
110 =  7 111 =  8 WUDP2:0 Specifies suspend time for system clock during PLL startup (after a speed instruction clears the
PLL bit in the SPDREG register) 000 =  128 µs
001 =  192 µs
010 =  320 µs
011 =  576 µs
100 =  1.088 ms
101 =  2.112 ms
110 =  4.160 ms 111 =  8.256 ms WUDX2:0 Specifies suspend time for system clock during OSC startup 000 =  320 µs
001 =  1.088 ms
010 =  4.160 ms
011 =  8.256 ms
100 =  16.448 ms
101 =  65.600 ms
110 =  524.352 ms 111 =  1048.64 ms