24 www.ubicom.com IP2022 Data Sheet 3.7 Clock Oscillator There are two clock oscillators, the OSC oscillator and the
RTCLK   oscillator.   The   OSC   oscillator   is   capable   of
operating  at  1  to  6  MHz  using  an  external  crystal  or
ceramic  resonator.  Using  the  PLL  clock  multiplier,  the
OSC clock is intended to provide the time base for running
the  CPU  core  at  speeds  up  to  100  MHz.  The  RTCLK
oscillator   operates   at   32.768   kHz   using   an   external
crystal. This oscillator is intended for running the real-time
timer when the OSC oscillator and PLL clock multiplier are
turned   off.   Either   clock   source   can   be   driven   by   an
external clock signal, up to 150 MHz for the OSC1 input
and up to 100 MHz for the RTCLK1 input. Figure   3-16   shows   the   clock   logic.   The   PLL   clock
multiplier has a fixed multiplication factor of 50. The PLL
is  preceded  by  a  divider  capable  of  any  integer  divisor
between 1 and 8, as controlled by the PIN2:0 bits of the
FUSE0 register. The PLL is followed by a second divider
capable   of   any   integer   divisor   between   1   and   4,   as
controlled by the POUT1:0 bits of the FUSE0 register. A
third divider which only affects the clock to the CPU core
is controlled by the speed change mechanism described
in Section 3.4. If both the OSC oscillator and PLL are re-
enabled simultaneously, the delay is controlled by only the
WUDX2:0   bits.   Bits   in   the   FUSE0   register   are   flash
memory   cells   which   cannot   be   changed   dynamically
during program execution. Figure 3-16  Clock Logic STATUS Bits 7:5 - 111
Bits 4:3 - 00
Bits 2:0 - 000 Bits 7:5 - 111
Bits 4:3 - 00
Bits 2:0 - 000 Bits 7:5 - 111
Bits 4:3 - 01
Bits 2:0 - 000 Bits 7:5 - 111
Bits 4:3 - 10
Bits 2:0 - 000 SPDREG 0x93 0x93 0x93 0x93 XCFG 0x01* 0x01* 0x01* 0x01* Global registers Undefined Unchanged Undefined Unchanged Data memory Undefined Unchanged Undefined Unchanged All I/O port registers except RxDIR    0x00 0x00 0x00 0x00 RxDIR registers 0xFF 0xFF 0xFF 0xFF All other registers Undefined Unchanged Undefined Unchanged * The FBUSY bit in the XCFG register is set while an instruction is fetched from flash memory and while the flash
memory is busy with a read, write, or erase operation. Table 3-7  Register States Following Reset (continued) Register Power-On RST Brown-Out Voltage      Watchdog
Timer Overflow 515-070.eps CPU Core
0-100 MHz Timer 2 RTTMR SERDES
Clock SPDREG Divider Postscaler Prescaler RTCLK Driver RTCLK1 Timer 0 RTCLK2 50X PLL Clock Multiplier  OSC
Driver OSC1 OSC2 System Clock PLL
Bypass Timer 1 ADC 50-300 MHz 1-6 MHz 0-100 MHz Crystal 1-6 MHz
Ext. 0-100 MHz FUSE0
Register FUSE0
Register 0-100 MHz speed Instruction speed Instruction Crystal 32.768 kHz
Ext. 0-100 MHz RTCFG Register