IP2022 Data Sheet www.ubicom.com 23 C1 should be chosen so that R2 × C1 exceeds the time
period  required  for  IOVDD  to  reach  a  valid  operating
voltage. 3.6.1 Brown-Out Detector The on-chip brown-out detection circuitry resets the CPU
when   AVdd                           dips   below   the   brown-out   voltage   level
programmed in the BOR2:0 bits of the FUSE1  register.
Bits in the FUSE1 register are flash memory cells which
cannot     be     changed     dynamically     during     program
execution. The device is held in reset as long as AVdd stays below
the brown-out  voltage.  The  CPU  will  come  out  of  reset
when   AVdd   rises   above   the   brown-out   voltage.   The
brown-out  level  can  be  programmed  using  the  BOR2:0
bits in the FUSE register, as shown in Table 3-6. 3.6.2 Reset and Interrupt Vectors After reset, the PC is loaded with 0xFFF0, which is near
the top of the program memory space. Typical activities
for the reset initialization code include: • Setting up the FCFG register with appropriate values
for flash timing compensation. • Issuing a speed instruction to initialize the CPU core
clock speed. • Checking for the cause of reset (brown-out voltage,
watchdog timer overflow, or other cause). In some ap-
plications, a “warm” reset allows some data initializa-
tion procedures to be skipped. • Copying  speed-critical  sections  of  code  from  flash
memory to program RAM. • Setting  up  data  memory  structures  (stacks,  tables,
etc.). • Initializing peripherals for operation (timers, etc.). • Initializing the dynamic interrupt vector and enabling
interrupts. Because the default interrupt vector location is 0, which is
in program RAM, interrupts should not be enabled until
the ISR is loaded in shadow RAM or the dynamic interrupt
vector  is  loaded  with  the  address  of  an  ISR  in  flash
memory. There is a single dynamic interrupt vector shared
by all interrupts. The interrupt vector can be changed by
loading  the  INTVECH  and  INTVECL  registers,  or  by
issuing a reti instruction with an option specifying that
the interrupt vector should be updated with the current PC
value. 3.6.3 Register States Following Reset The effect of different reset sources on a register depends
on  the  register  and  the  type  of  reset  operation.  Some
registers are initialized to specific values, some are left
unchanged, and some are undefined. A  register  that  starts  with  an  unknown  value  should  be
initialized by the software to a known value. Do not simply
test  the  initial  state  and  rely  on  it  starting  in  that  state
consistently.   Table 3-7   lists   the   IP2022   registers   and
shows  the  state  of  each  register  upon  reset,  with  a
different column for each type of reset. See Table 7-1 and
Table 7-2 for more detailed information. Table 3-6  Brown-Out Voltage Levels BOR2:0 Voltage 000 2.30V 001 2.25V 010 2.20V 011 2.15V 100 2.10V 101 2.05V 110 2.00V 111 Disabled Table 3-7  Register States Following Reset Register Power-On RST Brown-Out Voltage      Watchdog
Timer Overflow PCH (holds word address) 0xFF 0xFF 0xFF 0xFF PCL (holds word address) 0xF0 0xF0 0xF0 0xF0 CALLH (holds word address) 0xFF 0xFF 0xFF 0xFF CALLL (holds word address) 0xFF 0xFF 0xFF 0xFF