20 www.ubicom.com IP2022 Data Sheet To  re-enable  interrupts  during  ISR  execution,  the  ISR
code must first clear the source of the first interrupt. It may
also  be  desirable  to  disable  specific  interrupts  before
setting   the   GIE   bit   to   provide   interrupt   prioritization.
Caution must be taken not to exceed the interrupt shadow
register stack depth of 2. Clearing the GIE bit in the ISR cannot be used to globally
disable interrupts so that they remain disabled when the
ISR returns, because the reti instruction automatically
sets the GIE bit. To disable interrupts in the ISR so that
they remain disabled after the ISR returns, the individual
interrupt enable bits for each source of interrupts must be
cleared. 3.5.3 Interrupt    Latency    During    Speed
Change The interrupt latency is the time from the interrupt event
occurring  to  first  ISR  instruction  being  latched  from  the
decode to the execute stage. If the interrupt comes from a
Port B input and the SYNC bit in the FUSE1 register is 0,
an  additional  two  cycles  of  synchronization  delay  are
added to the interrupt latency. The  iread  or  iwrite  instructions  are  blocking  (i.e.
prevent  other  instructions  from  being  executed)  for  4
cycles.  If  these  instructions  are  used  in  mainline  code,
interrupt  latency  may  be  increased  by  an  additional  3
cycles. When an interrupt event is triggered, the CPU speed is
changed to the speed specified by the INTSPD register.
The SPDREG register is copied to a shadow register, then
loaded with the value from the INTSPD register. If the clock source for the system clock before the interrupt
is the same as after the interrupt (i.e. only the core divider
is modified), then the interrupt latency is deterministic with
respect  to  the  post-interrupt  CPU  clock.  The  interrupt
latency is 3 cycles for synchronous interrupts. For example, if the clock divisor is changed from 128 to 1
due to an interrupt then the interrupt latency is 3 cycles
with respect to the system clock. As another example, if the INTSPD register is configured
such that the system clock is the PLL and the clock divisor
is 1 (100 MIPS from 2 MHz) then the mainline code can
reduce the clock divisor down to a slower speed (e.g. a
clock divisor of 128) without affecting interrupt latency. If the clock source is changed, then the delay to change
the system clock will be up to one cycle of the slower of
the  pre-  and  post-interrupt  clocks.  The  total  interrupt
latency will be this delay plus the normal interrupt latency
(with respect to the new core clock). If  the  interrupt  speed  change  requires  re-enabling  the
clock multiplier PLL or crystal oscillator, then the interrupt
latency will be extended by the PLL or oscillator startup
delay.   These   delay   times   are   programmed   in   the
WUDP2:0  and  WUDX2:0  fields  of  the  FUSE0  register,
respectively. 3.5.4 Return From Interrupt The  reti  instruction  word  includes  three  bits  which
control its operation, as shown in Table 3-5. The three bits
are  specified  from  assembly  language  in  a  literal  (e.g. reti #0x7 to specify all bits as 1). Updating  the  interrupt  vector  allows  the  programmer  to
implement a sequential state machine. The next interrupt
will  resume  the  code  directly  after  the  previous  reti
instruction. The reti instruction takes 1 cycle to execute, and there
is a further delay of 2 cycles at the mainline code speed to
load the pipeline before the mainline code is resumed. clrb xcfg,7 instruction (inside ISR) Nothing, the GIE bit is
already clear setb xcfg,7 instruction (mainline code) Enable interrupts clrb xcfg,7 instruction (mainline code) Disable interrupts Table 3-4  GIE Bit Handling (continued) Event Effect Table 3-5  reti Instruction Options Bit Function 2 Reinstate the pre-interrupt speed
1 = enable, 0 = disable 1 Store the PC+1 value in the INTVECH and
INTVECL registers
1 = enable, 0 = disable 0 Add W to the T0TMR register
1 = enable, 0 = disable