IP2022 Data Sheet www.ubicom.com 19 On return from the ISR, these registers are restored from
the shadow registers, as shown in Figure 3-10. Figure 3-10  Interrupt Processing (On Return from the ISR) 3.5.2 Global Interrupt Enable Bit The GIE bit serves two purposes: • Preventing an interrupt in a critical section of mainline
code • Supporting nested interrupts The  GIE  bit  is  automatically  cleared  when  an  interrupt
occurs, to disable interrupts while the ISR is executing.
The GIE bit is automatically set by the reti instruction to
re-enable interrupts when the ISR returns. IPCH/IPCL Register W Register STATUS Register MULH Register                W
Shadow Register 1          STATUS
Shadow Register 1            MULH
Shadow Register 1 IPH/IPL Register DPH/DPL Register SPH/SPL Register ADDRSEL Register DATAH/DATAL Register           IPH/IPL
Shadow Register 1         DPH/DPL
Shadow Register 1         SPH/SPL
Shadow Register 1        ADDRSEL
Shadow Register 1    DATAH/DATAL
Shadow Register 1 515-069.eps PC INTVECH/INTVECL Register PC + 1      If reti
Instruction Bit 1 is Set                W
Shadow Register 2          STATUS
Shadow Register 2            MULH
Shadow Register 2           IPH/IPL
Shadow Register 2         DPH/DPL
Shadow Register 2         SPH/SPL
Shadow Register 2        ADDRSEL
Shadow Register 2    DATAH/DATAL
Shadow Register 2 SPDREG Register      If reti
Instruction Bit 2 is Set         SPDREG
Shadow Register 1         SPDREG
Shadow Register 2 T0TMR Register T0TMR + W      If reti
Instruction Bit 0 is Set      Table 3-4  GIE Bit Handling
Event Effect Enter ISR (interrupt) GIE bit is cleared Exit ISR
(reti instruction) GIE bit is set setb xcfg,7 instruction (inside ISR) Enable interrupts for
nested interrupt support