16 www.ubicom.com IP2022 Data Sheet 3.4.2 Instruction Timing All  instructions  that  perform  branches  take  3  cycles  to
complete, consisting of 1 cycle to execute and 2 cycles to
load the pipeline. In the case of an automatic speed change, the execution
time  will  be  with  respect  to  the  original  speed  and  the
pipeline load time will be with respect to the new speed. Conditional  branching  is  implemented  in  the  IP2022  by
using  conditional  skip  instructions  to  branch  over  an
unconditional  jump  instruction.  To  support  conditional
branching to other pages, the conditional skip instructions
will  skip  over two instructions if the  first  instruction  is  a page  instruction.  The  loadh  and  loadl  instructions also cause an additional instruction to be skipped. When
any of these conditions occur, it is called an extended skip instruction. Skip  instructions  take  1  cycle  if  they  do  not  skip,  or  2
cycles if they skip over one instruction. An extended skip
instruction may skip over more than one loadh, loadl,
or    page    instruction,    however    this    operation    is
interruptible and does not affect interrupt latency. The iread and iwrite instructions take 4 cycles. The
multiply instructions take 1 cycle. 3.5 Interrupt Support There are three types of interrupt sources: • On-Chip Peripherals–the serializer/deserializer units, real-time timer, timer 0, timer 1, and timer 2 are capa-
ble  of  generating  interrupts.  The  Parallel  Slave  Pe-
ripheral  does  not  generate  interrupts  on  its  own,
however it requires programming one of the Port B
external interrupt inputs to generate interrupts on its
behalf. • External Interrupts–the eight pins on Port B can be programmed to generate interrupts on either rising or
falling edges (see Section 5.1.1). • int Instruction–the int instruction can be executed by software to generate an interrupt. The INT_EN bit
in the XCFG register must be set to enable the int
instruction to trigger an interrupt. Because the reti
instruction returns to the int instruction, the INT_EN
bit  must  be  cleared  in  the  interrupt  service  routine
(ISR) before returning. Figure   3-8   shows   the   system   interrupt   logic.   Each
interrupt source has an interrupt enable bit. To be capable
of generating an interrupt, the interrupt enable bit and the
global interrupt enable (GIE) bit must be set. Table 3-3  Branch Timing Instruction Execution Time Pipeline Load Time jmp 1 2 call 1 2 ret 1 2 reti 1 2