14 www.ubicom.com IP2022 Data Sheet 3.3 Program Memory Figure 3-7 is a map of the program memory. A program
memory address in the INTVECH/INVECL, IPCH/IPCL, or
PCH/PCL registers or on  the  hardware stack is  a word
address.  However, the GNU software tools require byte addresses   when   referring   to   locations   in   program
memory. An address loaded in the ADDRX/ADDRH/ADDL register is a byte address. Figure 3-7  Program Memory Map The  program  memory  is  organized  as  8K-word  pages
(16K bytes). Single-instruction jumps and subroutine calls
are restricted to be within the same page. Longer jumps
and  calls  require  using  a  page  instruction  to  load  the
upper  address  bits  into  the  PA2:0  bits  of  the  STATUS
register. The page instruction must immediately precede
the jump or call instruction. The PA2:0 bits should not be
modified   by   writing   directly   to   the   STATUS   register,
because this may cause a mismatch between the PA2:0
bits  in  the  STATUS  register  and  the  current  program
counter (see Section 3.3.2). For more information about
the flash program memory, see Section 4.7. External memory is not shown in Figure 3-7 because the
CPU cannot execute instructions directly out of external
memory.  For  more  information  about  external  memory,
see Section 5.11. 3.3.1 Loading the Program RAM Software  loads  the  program  RAM  from  program  flash
memory using the iread/ireadi and iwrite/iwritei instructions. The iread instruction reads the 16-bit word specified by the address held in the
ADDRX/ADDRH/ADDRL  register.  This  word  can  be  in
program   flash   memory,   program   RAM,   or   external
memory.  When  the  iread  instruction  is  executed,  bits
15:8 of the word are loaded into the DATAH register, and
bits 7:0 are loaded into the DATAL register. The address
is a word-aligned byte address (i.e. an address that is zero
in  its  LSB).  The  ireadi  instruction  is  identical  to  the iread  instruction,  except  that  it  also  increments  the address by 2. The iwrite instruction writes the 16-bit word held in the
DATAH/DATAL  registers  to  the  program  RAM  location
specified by the address held in the ADDRX/ADDRH/ADDRL register. The iwritei instruction is identical, except that it also increments the
address    by    2.    For    more    information    about    the iread/ireadi  and  iwrite/iwritei  instructions, see Section 4.7. 3.3.2 Program Counter The  program  counter  holds  the  16-bit  address  of  the
instruction  to  be  executed.  The  lower  eight  bits  of  the
program  counter  are  held  in  the  PCL  register,  and  the
upper eight bits are held in the PCH register. A write to the
PCL  register  will  cause  a  jump  to  the  16-bit  address
specified  by  the  PCH  and  PCL  registers.  If  the  PCL
register is written as the destination of an add or addc
instruction    and    carry    occurs,    the    PCH    register    is
automatically incremented. (This may cause a mismatch
between the PA2:0 bits in the STATUS register and the
current    program    counter,    therefore    it    is    strongly
recommended that direct modification of the PCL register
is only used for jumps within a page.) The PCH register is
read-only. The PA2:0 bits in the STATUS register are not used for
address  generation,  except  when  a  jump  or  subroutine
call instruction is executed. However, when an interrupt is
taken, the PA2:0 bits are automatically updated with the
upper  three  bits  of  the  interrupt  vector.  These  bits  are
restored  from  the  STATUS  shadow  register  when  the
interrupt  service  routine  returns  (i.e.  executes  a  reti
instruction). 515-006.eps Program RAM Reserved 0x00000 15 0 0x04000 Flash Program Memory 0x14000 Flash Program Memory 0x18000 Flash Program Memory 0x1C000 Flash Program Memory 0x1FFFE 0x10000 0x0000 0x2000 0xA000 0xC000 0xE000 0xFFFF 0x8000    Byte
Address   Word
Address 0x03FFE 0x13FFE 0x17FFE 0x1BFFE 0x0FFFE 0x1FFF 0x9FFF 0xBFFF 0xDFFF 0x7FFF