IP2022 Data Sheet www.ubicom.com 13 The  XCFG  register  holds  additional  control  and  status
bits, as shown in Figure 3-5. • GIE—global interrupt enable bit. When set, interrupts are enabled. When clear, interrupts are disabled. For
more   information   about   interrupt   processing,   see
Section 3.5. • FWP—flash  write  protect  bit.  When  clear,  writes  to flash   memory   are   ignored.   For   more   information
about  programming  the  flash  memory,  see  Section
4.7. • RTEOS—real-time   timer   oversampling   enable   bit. When set, oversampling is used. For more informa-
tion, see Section 5.3. • RTOSC_EN—RTCLK   oscillator   enable   bit.   When clear, the RTCLK oscillator is operational. When set,
the RTCLK oscillator is turned off. • INT_EN—int instruction interrupt enable bit. When set,  int  instructions  cause  interrupts.  When  clear, int instructions only increment the PC, like nop. • FBUSY—read-only flash memory busy bit. Set while fetching  instructions  out  of  flash  memory  or  while
busy  processing  an  iread,  fwrite,  or  ferase
instruction,   otherwise   clear.   For   more   information
about  programming  the  flash  memory,  see  Section
4.7. The  PCH  and  PCL  register  pair  form  a  16-bit  program
counter. The  IPCH  and  IPCL  register  pair  specifies  the  return
address when a reti instruction is executed. The  INTVECH  and  INTVECL  register  pair  specifies  the
interrupt vector. It has a default value of 0 following reset.
On   a   return   from   interrupt,   an   option   of   the   reti
instruction allows software to save the incremented value
of  the  program  counter  in  the  INTVECH  and  INTVECL
registers. The  IPH  and  IPL  register  pair  is  used  as  a  pointer  for
indirect addressing. For more information about indirect
addressing, see Section 4.1.3. The DPH  and  DPL register pair  and the SPH and SPL
register pair are used as pointer registers for indirect-with-
offset  addressing.  For  more  information  about  indirect-
with-offset addressing, see Section 4.1.4. The SPH and
SPL registers are automatically post-decremented when
storing to memory with a push instruction, and they are automatically     pre-incremented     when     reading     from
memory with a pop instruction. The ADDRSEL register holds an index to one of eight 24-
bit pointers used to address program memory. The current
pointer selected by the ADDRSEL register is accessable
in  the   ADDRX  (bits  23:16),  ADDRH  (bits  15:8),  and
ADDRL (bits 7:0) registers. Program  memory  is  always  read  or  written  as  16-bit
words.  On  reads,  the  data  from  program  memory  is
loaded  into  the  DATAH  and  DATAL  register  pair.  On
writes, the contents of the DATAH and DATAL register pair
are loaded into the program memory. 3.2 Data Memory Figure  3-6  is  a  map  of  the  data  memory.  The  special-
purpose registers and the first 128 data memory locations
(between addresses 0x080 and 0x0FF) can be accessed
with  a  direct  addressing  mode  in  which  the  absolute
address of the operand is encoded within the instruction.
The  remaining  3840  bytes  of  data  memory  (between
addresses  0x100  and  0xFFF)  must  be  accessed  using
indirect or indirect-with-offset addressing modes. There is
one  16-bit  register  for  the  indirect  address  pointer,  and
two    16-bit    registers    for    indirect-with-offset    address
pointers.  The  offset  is  a  7-bit  value  encoded  within  the
instruction.  For  more  information  about  the  addressing
modes, see Section 4.1. Figure 3-6  Data Memory Map 7 6 5 4 3 2 1                                                                                                    0
GIE  FWP  RTEOS  RTOSC_EN  INT_EN  Rsvd  FBUSY Figure 3-5  XCFG Register 515-028.eps            128
Special-Purpose Registers   3840 Bytes
Data Memory 0x000 7 0 0x080 0xFFF            128
Global Registers 0x100 0x07F 0x0FF