12 www.ubicom.com IP2022 Data Sheet overflow or brown-out voltage detector). Figure 3-3 shows
the assignment of the bits in the STATUS register. • PA2:PA0—Program  memory page  select  bits. Used to extend the 13-bit address encoded in jump and call
instructions. Modified using the page instruction. • WD—Watchdog time-out bit. Set at reset, if reset was triggered   by   Watchdog   Timer   overflow,   otherwise
cleared. • BO—Brown-out  reset  bit.  Set  at  reset,  if  reset  was triggered by brown-out voltage level detection, other-
wise cleared. • Z—Zero bit. Affected by most logical, arithmetic, and data movement instructions. Set if the result was ze-
ro, otherwise cleared. • DC—Digit Carry bit. After addition, set if carry from bit 3   occurred,   otherwise   cleared.   After   subtraction,
cleared if borrow from bit 3 occurred, otherwise set. • C—Carry bit. After addition, set if carry from bit 7 of the result occurred, otherwise cleared. After subtrac-
tion, cleared if borrow from bit 7 of the result occurred,
otherwise  set.  After  rotate  (rr  or  rl)  instructions,
loaded with the LSB or MSB of the operand, respec-
tively. The MULH register receives the upper 8 bits of the 16-bit
product from signed or unsigned multiplication. The lower
8 bits are loaded into the W register. The  SPDREG  register  holds  bits  that  indicate  the  CPU
speed and clock source  settings loaded by  the  speed
instruction, as shown in Figure 3-4. The SPDREG register
is  read-only,  and  its  contents  may  only  be  changed  by
executing  a  speed  instruction,  taking  an  interrupt,  or
returning  from  an  interrupt.  For  more  information  about
the     speed     instruction     and     the     clock     throttling
mechanism, see Section 3.4 and Figure 3-16. • PLL—disable PLL clock multiplier; 1 = disabled. • OSC—disable  OSC  oscillator;  1  =  disabled  (stops
OSC oscillator and blocks propagation of OSC1 ex-
ternal clock input). • CLK1:0—selects the system clock source, as shown in Table 3-1. See Figure 3-16 for the clock logic. • CDIV3:0—selects the clock divisor used to generate the CPU core clock from the system clock, as shown
in Table 3-2 (also see Figure 3-16). The  INTSPD  register  holds  bits  that  control  the  CPU
speed and clock source during interrupt service routines.
It has the same format as the SPDREG register. 7 5 4 3 2 1 0 PA2:0 WD BO Z DC C Figure 3-3  STATUS Register 7 6 5 4 3 0 PLL OSC CLK1:0                                                  CDIV3:0
Figure 3-4  SPDREG Register               Table 3-1  CLK1:0 Field Encoding
CLK1:0 System Clock Source 00 PLL Clock Multiplier 01 OSC Oscillator/External OSC1 Input 10 RTCLK Oscillator/External RTCLK1 Input 11 System Clock Off Table 3-2  System Clock Divisor CDIV3:0 System  Clock
Divisor CPU Core Frequency (if System Clock is 100 MHz) 0000 1 100 MHz 0001 2 50 MHz 0010 3 33.3 MHz 0011 4 25 MHz 0100 5 20 MHz 0101 6 16.7 MHz 0110 8 12.5 MHz 0111 10 10 MHz 1000 12 8.33 MHz 1001 16 6.25 MHz 1010 24 4.17 MHz 1011 32 3.13 MHz 1100 48 2.08 MHz 1101 64 1.56 MHz 1110 128 0.78 MHz 1111 Clock Off 0 MHz