IP2022 Data Sheet www.ubicom.com 11 Although the philosophy followed in the design of Ubicom
products  emphasizes  the  use  of  fast  RISC  CPUs  with
predictable execution times to emulate peripheral devices
in software (called ipModules), there are a few hardware
peripherals which are difficult to emulate in software alone
(e.g. an A/D converter) or consume an excessive number
of instruction cycles when operating at high speed (e.g.
data   serialization/deserialization).   The   design   of   the
IP2022   incorporates   only   those   hardware   peripherals
which can greatly accelerate or extend the reach of the
ipModule concept. The hardware peripherals included on-
chip are: • 52 I/O port pins • Watchdog timer • Real-time timer • 2 Multifunction 16-bit timers with compare and cap-
ture registers • 2 Real-time 8-bit timers • 2 Serializer/deserializer (SERDES) units • 4 Linear feedback shift register (LFSR) units • 10-bit, 8-channel A/D converter • Analog comparator • Parallel slave peripheral interface There    is    a    single    interrupt    vector    which    can    be
reprogrammed by software. On-chip peripherals and up to
8 external inputs can raise interrupts. There are five sources of reset:
• RST external reset input • Power-On Reset (POR) logic • Brown-Out Reset (BOR) logic (detects low DVdd con-
dition) • Watchdog timer • In-system debugging/programming interface An   on-chip   PLL   clock   multiplier   enables   high-speed
operation  (up  to  100  MHz)  from  a  slow-speed  external
clock input, crystal, or ceramic resonator. A CPU clock-
throttling   mechanism   allows   fine   control   over   power
consumption  in  modes  that  do  not  require  maximum
speed, such as waiting for an interrupt. The IP2022 has a mechanism for in-system programming
of its flash and RAM program memories through a four-
wire SPI interface. This provides easy programming and
reprogramming of devices on assembled circuit boards. In
addition,   the   flash   memory   can   be   programmed   by
software  at  run  time,  for  example  to  store  user-specific
data  such  as  phone  numbers  and  to  receive  software
upgrades downloaded over the Internet. The IP2022 also
has   an   on-chip   debugging   facility   which   makes   the internal   operation   of   the   chip   visible   to   third-party
debugging tools. 3.1 CPU Registers Figure  3-2  shows  the  CPU  registers,  which  consist  of
seven 8-bit registers, seven 16-bit registers, and one 24-
bit register. The 16-bit registers are formed from pairs of
8-bit registers, and the 24-bit register is formed from three
8-bit registers. For the register quick reference guide, see
Section 7.0. Figure 3-2  CPU Registers The  W  or  working  register  is  used  as  the  source  or
destination for most arithmetic and logical instructions. The  STATUS  register  holds  the  condition  flags  for  the
results of arithmetic and logical operations, the page bits
(used  for  jumps  and  subroutine  calls),  and  bits  which
indicate  the  cause  of  the  last  reset  (watchdog  timer INTVECH/INTVECL Register W Register STATUS Register MULH Register SPDREG Register IPH/IPL Register DPH/DPL Register SPH/SPL Register DATAH/DATAL Register ADDRX/ADDRH/ADDRL Register 515-040.eps IPCH/IPCL Register 7 15 0 0 Interrupt Registers 15 0 Pointer Registers 15 0 Program Memory Interface Registers PCH/PCL Register 15 XCFG Register INTSPD Register ADDRSEL Register 23 7