IP2022 Data Sheet www.ubicom.com 101 7.3.18    TxCFG2H/TxCFG2L Register CPI2EN TxCPI2 enable bit 0 =   System clock enabled as clock           source for timer. TxCPI2 port
          pin available for general-pur-
          pose I/O.
1 =   TxCLK enabled as clock source for timer. Enabling this
bit does not make any other
restrictions on the use of the
port pin for general-purpose
I/O. CPI1EN TxCPI1 enable bit 0 =   Capture 1 input disabled.           TxCPI1 port pin available for
          general-purpose I/O.
1 =   TxCPI1 enabled as capture 1 input. Enabling this bit does not
make any other restrictions on
the use of the port pin for gen-
eral-purpose I/O. ECLKEDG TxCLK edge sensitivity select. (This bit is
ignored if the ECLKEN bit is clear.) 0 =   TxCLK increments timer on ris-           ing edge
1 =   TxCLK increments timer on fall- ing edge CAP1RST Reset timer on capture 1 event enable bit 0 =   Timer value unchanged by           occurrence of a capture 1
          event
1 =   Timer value cleared by occur- rence of a capture 1 event TMREN Timer enable bit 0 =   Timer disabled. Timer clock           source shut off to reduce power
          consumption.
1 =   Timer enabled Name Description 15 14 13 12 11 8 0 0 0 0 PS3:0 7 6 5 4 3 2 1 0 Name Description PS3:0 Timer prescaler divisor 0000 =   1
0001 =   2
0010 =   4
0011 =   8
0100 =   16
0101 =   32
0110 =   64  0111 =   128
1000 =   256
1001 =   512
1010 =   1024
1011 =   2048
1100 =   4096
1101 =   8192 1110 =   16384
1111 =   32768 TOUTSET Override bit to set the TxOUT output.
This bit always reads as zero. 0 =   Writing 0 to this bit has no           effect
1 =   Writing 1 to this bit forces the TxOUT signal high