100 www.ubicom.com IP2022 Data Sheet 7.3.17    TxCFG1H/TxCFG1L Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Description OFIE Timer overflow interrupt enable bit 0 =   Overflow interrupt disabled
1 =   Overflow interrupt enabled CAP2IE
or PWM mode: Compare 2 interrupt enable
bit CMP2IE Capture/Compare mode: Capture 2 inter-
rupt enable bit 0 =   Capture/Compare 2 interrupt           disabled
1 =   Capture/Compare 2 interrupt enabled CAP1IE Capture 1 interrupt enable bit 0 =   Capture 1 interrupt disabled
1 =   Capture 1 interrupt enabled CMP1IE Compare 1 interrupt enable bit 0 =   Compare 1 interrupt disabled
1 =   Compare 1 interrupt enabled OFIF Timer overflow interrupt flag 0 =   No timer overflow has occurred           since this bit was last cleared
1 =   Timer overflow has occurred CAP2IF
or PWM mode: Compare 2 interrupt flag (i.e.
timer value matched TxCMP2 value) CMP2IF Capture/Compare mode: Capture 2 flag
(i.e. TxCPI2 input triggered) 0 =   No capture/compare 2 event           has occurred since this bit was
          last cleared
1 =   Capture/compare 2 event has occurred CAP1IF Capture 1 interrupt flag 0 =   No capture 1 event has           occurred since this bit was last
          cleared
1 =   Capture 1 event has occurred CMP1IF Compare 1 interrupt flag 0 =   No compare 1 event has           occurred since this bit was last
          cleared
1 =   Compare 1 event has occurred MODE Timer mode select 0 =   PWM/timer mode
1 =   Capture/compare mode OEN TxOUT enable bit 0 =   TxOUT disabled. Port pin avail-           able for general-purpose I/O.
1 =   TxOUT enabled. Port pin must be configured for output in cor-
responding RxDIR register bit. ECLKEN TxCLK enable bit 0 =   TxCLK disabled. Port pin avail-           able for general-purpose I/O.
1 =   TxCLK enabled as clock source for timer. Enabling this
bit does not make any other
restrictions on the use of the
TxCLK port pin for general-pur-
pose I/O. Name Description