Instruction Set Architecture—IP2022 User’s Manual 80 www.ubicom.com third  instruction  is  decoded,  and  a  fourth  instruction  is  fetched.
Once the pipeline is full, instructions are executed at the rate of
one per clock cycle. Instructions that directly affect the contents of the program counter
(such as jumps and calls) require that the pipeline be cleared and
subsequently   refilled.   Therefore,   these   instructions   take   two
additional clock cycles. 3.4 Subroutine Call/Return Stack A  16-level  hardware  call/return  stack  is  provided  for  saving  the
program counter on a subroutine call and restoring the program
counter on subroutine return. The stack is not mapped into the
data  memory  address  space  except  for  the  top  level,  which  is
accessible as the CALLH and CALLL registers. Software can read
and write these registers to implement a deeper stack, in those
cases  which  require  nesting  subroutines  more  than  16  levels
deep. This stack is independent of the stack used with the push
and pop instructions and the SPH/SPL register. Table 3-2  Pipeline Execution Stage Cycle 1 Cycle 2 Cycle 3 Cycle 4 Fetch Instruction 1 Instruction 2 Instruction 3 Instruction 4 Decode Instruction 1 Instruction 2 Instruction 3 Execute Instruction 1 Instruction 2 Write Instruction 1