IP2022 User’s Manual—Instruction Set Architecture www.ubicom.com 79 3.2.8 System Control Instructions A system control instruction performs a special-purpose operation
that sets the operating mode of the IP2022 or reads data from the
program memory. Included in this category are the following types
of instructions: • speed—changes the CPU core speed (for saving power) • break—enters debug mode • page—writes the PA2:0 bits in the STATUS register • loadh/loadl—loads a 16-bit pointer into the DPH and DPL registers • iread/ireadi—reads a word from external memory, pro- gram flash memory, or program RAM • iwrite/iwritei—writes a word to the program RAM • fwrite—writes the flash program memory • ferase—erases the flash program memory • cwdt—clears the watchdog timer 3.3 Instruction Pipeline An instruction goes through a four-stage pipeline to be executed,
as shown in Figure 3-2. The first instruction is fetched from the
program  memory  on  the  first  clock  cycle.  On  the  second  clock
cycle, the first instruction is decoded and a second instruction is
fetched. On the third clock cycle, the first instruction is executed,
the  second  instruction  is  decoded,  and  a  third  instruction  is
fetched. On the fourth clock cycle, the first instruction’s results are
written to its destination, the second instruction is executed, the