Instruction Set Architecture—IP2022 User’s Manual 72 www.ubicom.com There   are   some   exceptions   to   this   behavior.   The   multiply
instructions always load the 16-bit product into the MULH and W
registers.  The  MULH  register  receives  the  upper  8  bits  of  the
product, and the W register receives the lower 8 bits. Traditionally single-operand instructions, such as increment, are
available in two forms distinguished by the D bit. When the D bit is
clear,  the  source  operand  is  specified  by  the  “fr”  field  and  the
destination operand is the W register. When the D bit is set, the
data memory location specified by the “fr” field is both the source
and destination operand. Also, there are a few cases of unrelated instructions, such as clr
and cmp, which are distinguished by the D bit. Figure 3-7  Two-Operand Instruction Format Figure  3-8  shows  the  immediate-operand  instruction  format.  In
this format, an 8-bit literal value is encoded in the instruction field.
Usually the W register is the destination operand, however this
format also includes instructions that use the top of the stack or a
special-purpose register as the destination operand. Figure 3-8  Immediate-Operand Format 15 10 9 8 0 Opcode D “fr” Field 15 8 7 0 Opcode 8-Bit Literal (“lit8”)