IP2022 User’s Manual—Instruction Set Architecture www.ubicom.com 71 3.2 Instruction Set The   instruction   set   consists   entirely   of   single-word   (16-bit)
instructions,  most  of  which  can  be  executed  at  a  rate  of  one
instruction  per  clock  cycle,  for  a  throughput  of  up to  100 MIPS
when executing out of program RAM. Assemblers may implement additional instruction mnemonics for
the convenience of programmers, such as a long jump instruction
which  compiles  to  multiple  IP2022  instructions  for  handling  the
page   structure   of   program   memory.   Refer   to   the   assembler
documentation    for    more    information    about    any    instruction
mnemonics implemented in the assembler. 3.2.1 Instruction Formats There are five instruction formats: • Two-operand arithmetic and logical instructions • Immediate-operand arithmetic and logical instructions • Jumps and subroutine calls • Bit operations • Miscellaneous instructions Figure  3-7  shows  the  two-operand  instruction  format.  The  two-
operand  instructions  perform  an  arithmetic  or  logical  operation
between the W register and a data memory location specified by
the “fr” field. The D bit indicates the destination operand. When the
D bit is clear, the destination operand is the W register. When the
D bit is set, the destination operand is specified by the “fr” field.