IP2022 User’s Manual—Instruction Set Architecture www.ubicom.com 63 3.1.1 Pointer Registers When an addition or increment instruction (i.e. add, addc, inc, incsz, or incsnz) on the low byte of a pointer register (i.e. IPL, DPL,  SPL,  or  ADDRL)  generates  a  carry,  the  high  part  of  the
register  is  incremented.  For  example,  if  the  IP  register  holds
0x00FF and an inc ipl instruction is executed, the register will
hold   0x0100   after   the   instruction.   When   a   subtraction   or
decrement   instruction   (i.e.   sub,   subc,   dec,   decsz,   or Table 3-1  Addressing Mode Summary “fr” Field Mode Assembler Syntax  Effective Address (EA)
and Range Restrictions 000000000    Indirect mov w,(ip)
mov (ip),w EA = IPH || IPL
0x020 < EA < 0xFFF 00nnnnnnn    Direct, special-
purpose
registers mov w,fr
mov fr,w EA = nnnnnnn
0x002 < EA < 0x07F 01nnnnnnn    Direct, global
registers mov w,fr
mov fr,w EA = 0x080 + nnnnnnn
0x080 < EA < 0x0FF 10nnnnnnn    Indirect with off-
set, data
pointer mov w,offset(dp)
mov offset(dp),w EA = DPH || DPL + nnnnnnn
0x000 < nnnnnnn < 0x07F
0x020 < EA < 0xFFF 11nnnnnnn    Indirect with off-
set, stack
pointer mov w,offset(sp)
mov offset(sp),w EA = SPH || SPL + nnnnnnn
0x000 < nnnnnnn < 0x07F
0x020 < EA < 0xFFF