3.0 IP2022 User’s Manual 61 Instruction Set Architecture The IP2022 implements a powerful load-store RISC architecture
with  a  rich  set  of  arithmetic  and  logical  operations,  including
signed  and  unsigned  8-bit  ×  8-bit  integer  multiply  with  a  16-bit
product. The CPU operates on data held in 128 special-purpose registers,
128 global registers, and 3840 bytes of data memory, shown in
Figure 3-1. The special-purpose registers are dedicated to control
and  status  functions  for  the  CPU  and  peripherals.  The  global
registers and data memory may be used for any functions required
by software, the only distinction among them being that the 128
global  registers  (addresses  0x080  to  0x0FF)  can  be  accessed
using a direct addressing mode. The remaining 3840 bytes of data
memory   (between   addresses   0x100   and   0xFFF)   must   be
accessed using indirect or indirect-with-offset addressing modes.
The  IPH/IPL  register  is  the  pointer  for  the  indirect  addressing
mode, and the DPH/DPL and SPH/SPL registers are the pointers
for the indirect-with-offset addressing modes.