System Architecture—IP2022 User’s Manual 58 www.ubicom.com 2.7.1 External Connections Figure 2-13 shows the connections for driving the OSC or RTCLK
clock  sources  with  an  external  signal.  To  drive  the  OSC  clock
source, the external clock signal is driven on the OSC1 pin and the
OSC2  pin  is  left  open.  The  external  clock  signal  driven  on  the
OSC1  pin  may  be  any  frequency  up  to  150  MHz.  To  drive  the
RTCLK  clock  source,  the  external  clock  signal  is  driven  on  the
RTCLK1 input and the RTCLK2 output is left open. The external
clock signal driven on the RTCLK1 pin may be any frequency up
to 100 MHz. Figure 2-13  External Clock Input RTCLK1   RTCLK2       Externally
Generated Clock Open 515-024.eps IP2022 OSC1 OSC2       Externally
Generated Clock Open