IP2022 User’s Manual—System Architecture www.ubicom.com 57 Figure 2-12  Clock Logic 515-070.eps CPU Core
0-100 MHz Timer 2 RTTMR SERDES
Clock SPDREG Divider Postscaler Prescaler RTCLK Driver RTCLK1 Timer 0 RTCLK2 50X PLL Clock Multiplier  OSC
Driver OSC1 OSC2 System Clock PLL
Bypass Timer 1 ADC 50-300 MHz 1-6 MHz 0-100 MHz Crystal 1-6 MHz
Ext. 0-100 MHz FUSE0
Register FUSE0
Register 0-100 MHz speed Instruction speed Instruction Crystal 32.768 kHz
Ext. 0-100 MHz RTCFG Register