System Architecture—IP2022 User’s Manual 56 www.ubicom.com 2.7 Clock Oscillator There are two clock oscillators, the OSC oscillator and the RTCLK
oscillator. The OSC oscillator is capable of operating at 1 to 6 MHz
using  an  external  crystal  or  ceramic  resonator.  Using  the  PLL
clock multiplier, the OSC clock is intended to provide the time base
for running the CPU core at speeds up to 100 MHz. The RTCLK
oscillator operates at 32.768 kHz using an external crystal. This
oscillator is intended for running the real-time timer when the OSC
oscillator  and  PLL  clock  multiplier  are  turned  off.  Either  clock
source can be driven by an external clock signal, up to 150 MHz
for the OSC1 input and up to 100 MHz for the RTCLK1 input. Figure 2-12 shows the clock logic. The PLL clock multiplier has a
fixed multiplication factor of 50. The PLL is preceded by a divider
capable of any integer divisor between 1 and 8, as controlled by
the PIN2:0 bits of the FUSE0 register. The PLL is followed by a
second divider capable of any integer divisor between 1 and 4, as
controlled  by  the  POUT1:0  bits  of  the  FUSE0  register.  A  third
divider which only affects the clock to the CPU core is controlled
by the speed change mechanism described in Section 2.4. If both
the  OSC  oscillator  and  PLL  are  re-enabled  simultaneously,  the
delay is controlled by only the WUDX2:0 bits. Bits in the FUSE0
register   are   flash   memory   cells   which   cannot   be   changed
dynamically   during   program   execution.   For   more   information
about the FUSE0 register, see Section 6.2.