IP2022 User’s Manual—System Architecture www.ubicom.com 55 Data memory Undefined Unchanged Undefined Unchanged All I/O port reg-
isters except
RxDIR 0x00 0x00 0x00 0x00 RxDIR regis-
ters 0xFF 0xFF 0xFF 0xFF All other regis-
ters Undefined Unchanged Undefined Unchanged * The FBUSY bit in the XCFG register is set while an instruction is fetched
from flash memory and while the flash memory is busy with a read, write, or
erase operation. Table 2-5  Register States Following Reset Register Power-On      RST
Asserted Brown-Out Voltage   Watchdog
Timer Over- flow