IP2022 User’s Manual—System Architecture www.ubicom.com 53 2.6.2 Reset and Interrupt Vectors After reset, the PC is loaded with 0xFFF0, which is near the top of
the   program   memory   space.   Typical   activities   for   the   reset
initialization code include: • Setting up the FCFG register with appropriate values for flash
timing compensation. • Issuing a speed instruction to initialize the CPU core clock
speed. • Checking for the cause of reset (brown-out voltage, watchdog
timer overflow, or other cause). In some applications, a “warm”
reset allows some data initialization procedures to be skipped. • Copying speed-critical sections of code from flash memory to
program RAM. • Setting up data memory structures (stacks, tables, etc.). • Initializing peripherals for operation (timers, etc.). • Initializing  the  dynamic  interrupt  vector  and  enabling  inter-
rupts. Because the default interrupt vector location is 0x0000, which is in
shadow RAM, interrupts should not be  enabled until the ISR is
loaded in shadow RAM or the dynamic interrupt vector is loaded
with  the  address  of  an  ISR  in  flash  memory.  There  is  a  single
dynamic  interrupt  vector  shared  by  all  interrupts.  The  interrupt
vector can be changed by loading the INTVECH and INTVECL
registers, or by issuing a reti instruction with an option specifying
that the interrupt vector should be updated with the current PC
value.