System Architecture—IP2022 User’s Manual 50 www.ubicom.com However, Figure 2-10 depicts a situation in which IOVDD rises too
slowly.  In  this  scenario,  the  startup  timer  will  time  out  prior  to
IOVDD reaching a valid operating voltage level (IOVDD min). This
means the CPU will come out of reset and start operating with the
supply voltage below the level required for reliable performance.
In this situation, an external RC circuit is recommended for driving
RST. The RC delay should exceed the time period required for
IOVDD to reach a valid operating voltage. Figure 2-10  IOVDD Rise Time Exceeds Tstartup IOVDD RST POR Tstartup Startup Timer (Time-Out)         Internal
Rest Signal 515-020.eps