System Architecture—IP2022 User’s Manual 46 www.ubicom.com • Brown-out voltage reset • RST external reset The  first  two  sources  listed  above  do  not  reset  the  chip,  so
program execution continues from where it was stopped. The last
three sources reset the chip, so software must perform all of its
reset initialization tasks to recover. This usually requires additional
time, as compared to recovery through an external interrupt. 2.6 Reset There are five sources of reset: • Power-On Reset • Brown-Out Reset • Watchdog Reset • External Reset (from the RST pin) • Target Reset (from the debugging interface) Each  of  these  reset  conditions  causes  the  program  counter  to
branch to the top of the program memory (word address FFF0). The IP2022 incorporates a Power-On Reset (POR) detector that
generates  an  internal  reset  as  IOVDD  rises  during  power-up.
Figure 2-7 is a block diagram of the reset logic. It includes a 10-bit
startup timer and a reset latch. The startup timer controls the reset
time-put delay. The reset latch controls the internal reset signal.
On power-up, the reset latch is set (CPU held in reset), and the
startup timer starts counting once it detects a valid logic high signal
on the RST pin. Once the startup timer reaches the end of the