System Architecture—IP2022 User’s Manual 44 www.ubicom.com 2.5.4 Return From Interrupt The  reti instruction word includes three bits which  control its
operation. Updating the interrupt vector allows the programmer to implement
a  sequential  state  machine.  The  next  interrupt  will  resume  the
code directly after the previous reti instruction. The  reti  instruction  takes  1  cycle  to  execute,  and  there  is  a
further delay of 2 cycles at the mainline code speed to load the
pipeline before the mainline code is resumed. Table 2-3  reti Instruction Options Bit Function 2 Reinstate the pre-interrupt speed
1 = enable, 0 = disable 1 Store the PC+1 value in the INTVECH and INTVECL
registers
1 = enable, 0 = disable 0 Add W to the T0TMR register
1 = enable, 0 = disable