IP2022 User’s Manual—System Architecture www.ubicom.com 43 If the clock source for the system clock before the interrupt is the
same as after the interrupt (i.e. only the core divider is modified),
then the interrupt latency is deterministic with respect to the post-
interrupt   CPU   clock.   The   interrupt   latency   is   3   cycles   for
synchronous interrupts. For example, if the clock divisor is changed from 128 to 1 due to
an interrupt, then the interrupt latency is 3 cycles with respect to
the post-interrupt clock. As another example, if the INTSPD register is configured such that
the system clock comes from the PLL and the clock divisor is 1
(100 MIPS from 2 MHz), then the mainline code can reduce the
clock divisor to a slower speed (e.g. a clock divisor of 128) without
affecting the interrupt latency. If  the  clock  source  is  changed,  then  the  delay  to  change  the
system clock will be up to one cycle of the slower of the pre- and
post-interrupt clocks. The total interrupt latency will be this delay
plus  the  normal  interrupt  latency  (with  respect  to  the  new  core
clock). If  the  interrupt  speed  change  requires  re-enabling  the  clock
multiplier PLL or crystal oscillator, then the interrupt latency will be
extended  by  the  PLL  or  oscillator  startup  stabilization  period.
These   delay   times   are   programmed   in   the   WUDP2:0   and
WUDX2:0 fields of the FUSE0 register, respectively.