System Architecture—IP2022 User’s Manual 42 www.ubicom.com to disable specific interrupts before setting the GIE bit to provide
interrupt prioritization. Caution must be taken not to exceed the
interrupt shadow register stack depth of 2. Clearing the GIE bit in the ISR cannot be used to globally disable
interrupts  so  that  they  remain  disabled  when  the  ISR  returns,
because the reti instruction automatically sets the GIE bit. To
disable interrupts in the ISR so that they remain disabled after the
ISR returns, the individual interrupt enable bits for each source of
interrupts must be cleared. 2.5.3 Interrupt Latency The interrupt latency is the time from the interrupt event occurring
to  first  ISR  instruction  being  latched  from  the  decode  to  the
execute stage. If the interrupt comes from a Port B input and the
SYNC bit in the FUSE1 register is 0, an additional two cycles of
synchronization delay are added to the interrupt latency. The  iread  or  iwrite  instructions  are  blocking  (i.e.  prevent
other  instructions  from  being  executed)  for  4  cycles.  If  these
instructions are used in mainline code, interrupt latency may be
increased by an additional 3 cycles. When an interrupt event is triggered, the CPU speed is changed
to  the  speed  specified  by  the  INTSPD  register.  The  SPDREG
register is copied to a shadow register, then loaded with the value
from the INTSPD register.