IP2022 Users ManualSystem Architecture
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2.5.2
Global Interrupt Enable Bit
The GIE bit serves two purposes:
Preventing an interrupt in a critical section of mainline code
Supporting nested interrupts
The GIE bit is automatically cleared when an interrupt occurs, to
disable interrupts while the ISR is executing. The GIE bit is
automatically set by the reti instruction to re-enable interrupts
when the ISR returns.
To re-enable interrupts during ISR execution, the ISR code must
first clear the source of the first interrupt. It may also be desirable
Table 2-2 GIE Bit Handling
Event
Effect
Enter ISR (interrupt)
GIE bit is cleared
Exit ISR (reti instruction)
GIE bit is set
setb xcfg,7 instruction (inside ISR)
Enable interrupts for
nested interrupt
support
clrb xcfg,7 instruction (inside ISR)
Nothing, the GIE bit
is already clear
setb xcfg,7 instruction
(mainline code)
Enable interrupts
clrb xcfg,7 instruction
(mainline code)
Disable interrupts