System Architecture—IP2022 User’s Manual 40 www.ubicom.com Figure 2-6  Interrupt Processing (On Return from the ISR) IPCH/IPCL Register W Register STATUS Register MULH Register               W
Shadow Register 1          STATUS
Shadow Register 1            MULH
Shadow Register 1 IPH/IPL Register DPH/DPL Register SPH/SPL Register ADDRSEL Register DATAH/DATAL Register           IPH/IPL
Shadow Register 1         DPH/DPL
Shadow Register 1         SPH/SPL
Shadow Register 1        ADDRSEL
Shadow Register 1    DATAH/DATAL
Shadow Register 1 515-069.eps PC INTVECH/INTVECL Register PC + 1      If reti
Instruction Bit 1 is Set               W
Shadow Register 2          STATUS
Shadow Register 2            MULH
Shadow Register 2           IPH/IPL
Shadow Register 2         DPH/DPL
Shadow Register 2         SPH/SPL
Shadow Register 2        ADDRSEL
Shadow Register 2    DATAH/DATAL
Shadow Register 2 SPDREG Register      If reti
Instruction Bit 2 is Set         SPDREG
Shadow Register 1         SPDREG
Shadow Register 2 T0TMR Register T0TMR + W      If reti
Instruction Bit 0 is Set