System Architecture—IP2022 User’s Manual 36 www.ubicom.com Figure 2-4  System Interrupt Logic 515-067.eps Interrupt
to CPU Port B Interrupt Serializer/Deserializer Interrupt Timer 0 Overflow Interrupt                                 T0IE Bit
Real-TIme Timer Interrupt RTIE Bit Timer 1 Compare Interrupt                         T1CMP1IE Bit
Timer 1 Capture 1 Interrupt                                         T1CAP1TIE Bit
Timer 1 Compare/Capture 2 Interrupt  T1CMP2IE/T1CAP2IE Bit
Timer 1 Overflow Interrupt T1OFIE Bit Timer 2 Compare 1 Interrupt T2CMP1IE Bit int Instruction GIE Bit Timer 2 Capture 1 Interrupt                                           T2CAP1IE Bit
Timer 2 Compare/Capture 2 Interrupt  T2CMP2IE/T2CAP2IE Bit
Timer 2 Overflow Interrupt T2OFIE Bit INT_EN Bit