IP2022 User’s Manual—System Architecture www.ubicom.com 35 however this operation is interruptible and does not affect interrupt
latency. The iread and iwrite instructions take 4 cycles. The multiply
instructions take 1 cycle. 2.5 Interrupt Support There are three types of interrupt sources: • On-Chip   Peripherals–the   serializer/deserializer   (SERDES)
units, real-time timer, timer 0, timer 1, and timer 2 are capable
of generating interrupts. The Parallel Slave Peripheral does
not generate interrupts on its own, however it requires pro-
gramming one of the Port B external interrupt inputs to gener-
ate interrupts on its behalf. • External  Interrupts–the  eight  pins  on  Port  B  can  be  pro-
grammed to generate interrupts on either rising or falling edg-
es (see Section 4.1.1). • int Instruction–the int instruction can be executed by soft- ware to generate an interrupt. The INT_EN bit in the XCFG
register must be set to enable the int instruction to trigger an
interrupt. Because the reti instruction returns to the int in-
struction, the INT_EN bit must be cleared in the interrupt ser-
vice routine (ISR) before returning. Figure 2-4 shows the system interrupt logic. Each interrupt source
has  an  interrupt  enable  bit.  To  be  capable  of  generating  an
interrupt, the interrupt enable bit and the global interrupt enable
(GIE) bit must be set.