IP2022 User’s Manual—System Architecture www.ubicom.com 33 2.4.1 Speed Change Delay The automatic speed changes require a certain amount of delay
to take effect: • Changing the Clock Divisor—there is no delay when the clock
divisor is changed. • Changing the Clock Source—the delay is up to one cycle of
the slower clock. For example, changing between 32 kHz and
100 MHz could require up to 31.25 microseconds. • Turning on the OSC Clock Oscillator (clearing the OSC bit in
the  SPDREG  register)—the  system  clock  suspend  time  is
specified in the WUDX2:0 bits in the FUSE0 register. • Turning on the PLL Clock Multiplier (clearing the PLL bit in the
SPRDREG register)—the system clock suspend time is spec-
ified in the WUDP2:0 bits in the FUSE0 register. If both the OSC oscillator and PLL are re-enabled simultaneously,
the  delay  is  controlled  by  only  the  WUDX2:0  bits.  Bits  in  the
FUSE0 register are flash memory cells which cannot be changed
dynamically during program execution (see Section 6.2).