System Architecture—IP2022 User’s Manual 32 www.ubicom.com The  SPDREG  register  holds  the  current  settings  for  the  clock
divisor,  clock  source,  and  disable  bits.  These  settings  can  be
explicitly  changed  by  executing  a  speed  instruction,  and  they
change automatically on interrupts. The SPDREG register is read-
only, and its contents may only be changed by executing a speed
instruction, taking an interrupt, or returning from an interrupt. Two
consecutive  speed  instructions  are  not  allowed.  The  INTSPD
register   specifies   the   settings   used   during   execution   of   the
interrupt  service  routine.  The  INTSPD  register  is  both  readable
and writeable. On return from interrupts, the reti instruction includes a bit that
specifies whether the pre-interrupt speed is restored or the current
speed is maintained. The actual speed of the CPU is indicated by the SPDREG register
unless the specified speed is faster than the flash access time and
the program is executing out of flash. When program execution
moves  from  program  RAM  to  program  flash  memory,  the  new
clock  divisor  will  be  the  greater  (slower)  of  the  clock  divisor
indicated by the SPDREG register and the clock divisor required
to avoid violating the flash memory access time. The SPDREG
register does not indicate if the flash clock divisor is being used.
The value indicated by the SPDREG will be overridden only if the
speed is too fast for the flash memory. The FCFG register holds bits that specify the minimum number of
system  clock  cycles  for  each  flash  memory  cycle  (see  Section
3.7).