IP2022 User’s Manual—System Architecture www.ubicom.com 31 2.4 Low Power Support Software can change the execution speed of the CPU to reduce
power consumption. A mechanism is provided for automatically
changing the speed on entry and return from the interrupt service
routine.  The  speed  instruction  specifies  power-saving  modes
that include a clock divisor between 1 and 128. This divisor only
affects  the  clock  to  the  CPU  core,  not  the  timers  or  ADC  (see
Figure  2-12).  The  speed  instruction  also  specifies  the  clock
source (OSC clock, RTCLK oscillator, or PLL clock multiplier) and
whether to disable the OSC clock oscillator or the PLL. The next
two instructions after switching the clock source will be run at the
old speed. The speed instruction executes using the current clock divisor.
The new clock divisor takes effect with the following instruction, as
shown in the following code example. Before executing the speed instruction, check that the FBUSY bit
in  the  XCFG  register  is  clear  and  that  the  FCFG  register  has
appropriate settings for the new clock frequency. nop ;assume divisor is 4, so this
;instruction takes 4 cycles speed     #$06 ;change the divisor to 8,
;instruction takes 4 cycles nop ;instruction takes 8 cycles speed     #$0D ;change the divisor to 1,
;instruction takes 8 cycles nop ;instruction takes 1 cycle