Register Quick Reference—IP2022 User’s Manual 428 www.ubicom.com C.3.18   TxCFG2H/TxCFG2L Register CAP1RST Reset timer on capture 1 event enable bit 0 =    Timer value unchanged by occurrence of a capture 1           event
1 =    Timer value cleared by occurrence of a capture 1 event TMREN Timer enable bit 0 =    Timer disabled. Timer clock source shut off to reduce           power consumption.
1 =    Timer enabled Name Description 15 14 13 12 11 8 0 0 0 0 PS3:0 7 6 5 4 3 2 1 0 Reserved TOUTSET TOUTCLR CPI2CPI1    CPI2EDG1:0 CPI1EDG1:0 Name Description PS3:0 Timer prescaler divisor 0000 =   1
0001 =   2
0010 =   4
0011 =   8
0100 =   16
0101 =   32