IP2022 User’s Manual—Register Quick Reference
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425
C.3.17 TxCFG1H/TxCFG1L Register
T0IF
Timer 0 interrupt flag
0 = No timer overflow has occurred since this bit was
last cleared
1 = Timer overflow has occurred
Name
Description
15
14
13
12
11
10
9
8
OFIE
CAP2IE
CMP2IECAP1IE CMP1IE
OFIF
CAP2IF
CMP2IFCAP1IF CMP1IF
7
6
5
4
3
2
1
0
MODE
OEN ECLKEN CPI2EN CPI1EN ECLKEDG CAP1RST TMREN
Name
Description
OFIE
Timer overflow interrupt enable bit
0 = Overflow interrupt disabled
1 = Overflow interrupt enabled
CAP2IE
PWM mode: Compare 2 interrupt enable bit
CMP2IE
Capture/Compare mode: Capture 2 interrupt enable bit
0 = Capture/Compare 2 interrupt disabled
1 = Capture/Compare 2 interrupt enabled
