IP2022 User’s Manual—Register Quick Reference www.ubicom.com 409 C.3.5 INTSPD Register 7 6 5 4 3 0 PWRD1:0 CLK1:0 CDIV3:0 Name Description PWRD1 Controls PLL clock multiplier operation. If the PLL is not
required, power consumption can be reduced by disabling it. 0 =   PLL clock multiplier enabled
1 =   PLL clock multiplier disabled PWRD0 Controls OSC oscillator operation. If the oscillator is not
required, power consumption can be reduced by disabling it. 0 =   OSC oscillator enabled
1 =   OSC oscillator disabled CLK1:0 Selects the system clock source. 00 =   PLL clock multiplier
01 =   OSC oscillator/external clock on OSC1 input
10 =   RTCLK oscillator/external clock on RTCLK1 input
11 =   System clock disabled (off)