Register Quick Reference—IP2022 User’s Manual 408 www.ubicom.com FWRT3:0 The flash memory erase and write timing is derived from the
CPU core clock through a programmable divider. The
FWRT3:0 bits specify the divisor. The time base must be 1 to 2
microseconds. Below 1 microsecond, the flash memory will be
underprogrammed, and data retention is not guaranteed.
Above 2 microseconds, the flash memory will be overpro-
grammed, and reliability is not guaranteed. 0000 =   2
0001 =   3
0010 =   4
0011 =   6
0100 =   8
0101 =   12
0110 =   16  0111 =   24
1000 =   32
1001 =   48
1010 =   64
1011 =   96
1100 =   128
1101 =   192 1110 =   256
1111 =   384 Name Description