IP2022 User’s Manual—Register Quick Reference www.ubicom.com 407 FRDTC1:0 The number of CPU core cycles for reading the flash memory
using an iread instruction must be specified to prevent the
flash memory access time from being exceeded. Because the
CPU core is subject to changes in speed, the value pro-
grammed in these bits should be appropriate for the fastest
speed that might be used (typically, the faster of the main line
code and the interrupt service routine). The FRDTC1:0 bits
specify the number of CPU core clock cycles required for read
access. 00 =   1 cycle
01 =   2 cycles
10 =   3 cycles
11 =   4 cycles Name Description