Register Quick Reference—IP2022 User’s Manual 398 www.ubicom.com 0x075 S2RCNT SERDES 2 received bit count
(actual) (read-only) 00000000 0x079 S2RSYNC SERDES 2 receive bit sync pattern 00000000 0x07D S2SMASK SERDES 2 receive sync mask 00000000 0x072 S2TBUFH SERDES 2 transmit buffer (high
byte) Undefined 0x073 S2TBUFL SERDES 2 transmit buffer (low byte) Undefined 0x074 S2TCFG SERDES 2 transmit configuration 00000000 0x070 S2TMRH SERDES 2 clock timer register (high
byte) 00000000 0x071 S2TMRL SERDES 2 clock timer register (low
byte) 00000000 0x00E SPDREG Current speed (read-only) 10010011 0x006 SPH Stack Pointer (high byte) 00000000 0x007 SPL Stack Pointer (low byte) 00000000 0x00B STATUS STATUS register On POR or
RST Reset: 11100000 OnBrown-out
Reset: 11101000 On WDT
Overflow: 11110000 Table C-2  Register Addresses and Reset State (continued) Address Name Description Reset
Value