Similarities with SX-Series Devices—IP2022 User’s Manual 374 www.ubicom.com for  specifying  a  call  destination  within  the  first  half  of  a  512-
instruction page. The IP2022 uses 13-bit fields for each, resulting
in a page size of 8192 instructions. Call/Return  Stack—The  depth  of  the  hardware  call/return  stack
has been increased from 8 levels on the SX-Series devices to 16
levels on the IP2022. The top of the stack is mapped into data
memory,   so   software   can   extend   the   stack   depth   for   those
applications which require more deeply nested subroutines. Carry/Borrow—The    SX-Series    devices    had    a    fuse    bit    to
distinguish between add and addc (add-with-carry) instructions.
The IP2022 implements separate add and addc instructions, as
well as the corresponding sub and subc instructions. Interrupt Processing—The SX-Series devices disabled interrupts
during  the  execution  of  the  interrupt  service  routine  (ISR).  The
IP2022 allows re-enabling interrupts in the ISR, and it provides a
2-level stack for saving critical registers during nested interrupts. STATUS Register Bits—The power-down bit (PD) and time-out bit
(TO) have been renamed the brown-out bit (BO) and watchdog bit
(WD), respectively. Functionally, the WD bit differs from the TO bit
in that the cwdt instruction does not automatically clear the WD
bit. Low-Power Support—The SX-Series devices had a sleep mode
which only could be exited by a device reset. The IP2022 does not
have a sleep mode, but it supports clock throttling and clock-stop
modes. The IP2022 can exit from these modes in response to an
external interrupt or an on-chip interrupt from the real-time timer.