IP2022 User’s Manual—System Architecture www.ubicom.com 23 2.1.2 SPDREG Register 7 6 5 4 3 0 PLL OSC CLK1:0 CDIV3:0 Name Description PLL Controls PLL clock multiplier operation. If the PLL is not
required, power consumption can be reduced by disabling it. 0 =   PLL clock multiplier enabled
1 =   PLL clock multiplier disabled OSC Controls OSC oscillator operation. If the oscillator is not
required, power consumption can be reduced by disabling it. 0 =   OSC oscillator enabled
1 =   OSC oscillator disabled CLK1:0 Selects the system clock source. 00 =   PLL clock multiplier
01 =   OSC oscillator/external clock on OSC1 input
10 =   RTCLK oscillator/external clock on RTCLK1 input
11 =   System clock disabled (off)