A.0 IP2022 User’s Manual 373 Similarities with SX-Series Devices This appendix summarizes the significant differences between the
operation of SX-Series devices and the IP2022. Instruction  Format—The  12-bit  instruction  formats  on  the  SX-
Series  devices  have  been  extended  to  16-bit  formats  on  the
IP2022, as shown below. (A, B, C, D,  and E  represent  opcode
bits.) Most SX-Series instructions have an equivalent IP2022 instruction
in the 16-bit format. An important feature of the 16-bit format is the
extension of the “fr” field from five bits to nine bits. Register Banks—The register banking scheme used in the SX-
Series devices has been discarded in favor of a uniform address
space. Register banking can be simulated by using the IPH/IPL
pointer register to emulate the FSR register. Page Size—The SX-Series devices had a 9-bit field for specifying
a jump destination within a 512-instruction page, and an 8-bit field Instruction Type SX-Series Instruction IP2022 Instruction Register Operation 00AB CDEf ffff 00AB CDEf ffff ffff Bit Operation 01AB bbbf ffff 10AB bbbf ffff ffff 8-bit Literal Operation 1ABC kkkk kkkk 0111 1ABC kkkk kkkk