IP2022 User’s Manual—In-System Programming www.ubicom.com 367 6.2.2 FUSE1 Register 15 14 13 7 6 4 3 2 0 CP  SYNC Reserved BOR2:0 WDTE WDIV2:0 Name Description CP Clear to enable code protection. Once cleared, this bit cannot
be set until the entire device is erased. When code protection
is enabled, program memory reads as all 0 to an external
device programmer. This bit does not affect access to program
flash memory made by software, using the iread instruction.
In-system debugging is not available when code protection is
enabled. Code protection does not protect the configuration
block against reading. 0 =   Enabled
1 =   Disabled SYNC Set to read directly from the port pins through the RxIN regis-
ter, clear to read through a synchronization register. This bit
should be clear if any external devices that can be read from
I/O port pins are running asynchronously to the CPU core
clock. 0 =   Enabled
1 =   Disabled