In-System Programming—IP2022 User’s Manual 364 www.ubicom.com 6.2.1 FUSE0 Register 15 14 13 12 11 9 8 6 5 3 2 0 XTAL  RTCLK  POUT1:0 PIN2:0 Reserved WUDP2:0 WUDX2:0 Name Description XTAL OSC2 crystal drive output. Output must be disabled if an
external clock signal is driven on OSC1 input. 0 =   Enabled
1 =   Disabled RTCLK RTCLK2 crystal drive output. Output must be disabled if an
external clock signal is driven on RTCLK1 input. 0 =   Enabled
1 =   Disabled POUT1:0 Specifies PLL clock multiplier postscaler divisor. 00 =   1
01 =   2
10 =   3
11 =   4